1. Field of the Invention
This invention relates to integrated circuits and more particularly relates to an apparatus and method of using shared process steps to fabricate one or more separated, elevated substrates suitable for circuit element fabrication and one or more local interconnects to connect conductive circuit device elements.
2. Description of the Related Art
Integrated circuits and the systems which utilize them have become ubiquitous throughout the world. A typical wafer includes integrated circuits having a large number of circuit devices such as insulated gate field effect transistors (IGFETs) and other circuit devices which are fabricated on a single substrate, normally silicon. Referring to FIG. 1, fabrication of the multilevel interconnect structure of integrated circuit 100 is preceded by the fabrication of an exemplary N-channel IGFET 101. IGFET 101 includes field oxide isolation regions 120 and 122 which are formed in substrate 110 to isolate the IGFET 101 from adjacent devices (not shown). The IGFET 101 of conventional integrated circuit 100 uses a polysilicon gate 102, separated from the substrate 110 by a thin insulating layer 112, to control an underlying channel 104 which joins doped source/drain 106 and source/drain 108. The source/drain 106 and source/drain 108 are doped oppositely to the channel 104 and the substrate 110. The operation of the IGFET 101 involves application of an input voltage to the gate 102, which sets up a transverse electric field in the channel 104 to modulate the conductance of the channel 104 between source/drain 106 and source/drain 108.
Following fabrication of the IGFET 101, an insulation layer 114 made of chemical vapor deposition (CVD) silicon dioxide, for example, is conformally formed over the IGFET 101 and substrate 110. Contact holes (also referred to as `windows`) are then typically opened through the insulation layer prior to formation of the overlying thin film interconnects 116 and 118 and filled with a conductive film to form contacts 103a and 103b. IGFET 101 is interconnected with other circuit devices (not shown), generally using high conductivity, thin film structures, such as metal interconnects 116 and 118, which are patterned above insulation layer 114. Contacts 103a and 103b electrically connect interconnects 116 and 118 with source/drain 106 and source/drain 108, respectively.
The fabrication of other IGFETs (not shown) in substrate 110 may be similarly carried out while utilizing appropriate isolation techniques. Additionally, higher order multilevel interconnect structures may be fabricated to facilitate desired connectivity.
Although there is much variation in particular device structures and process techniques, conventional integrated circuit fabrication techniques generally focus upon single device layers with multilevel interconnect structures limits, for example, design flexibility and density.